Integrated circuits (ICs), such as very large scale integration (VLSI) chips like microprocessors, depend on precise timing to coordinate activity throughout the IC. Typically, an internal clock is distributed throughout the chip to synchronously capture incoming data at the register latches and launch data from register latches. While the edge of the internal clock should arrive at all the register latches simultaneously to trigger the register latches simultaneously, differences in chips can cause the edge of the internal clock to arrive at different register latches at different times and create timing uncertainties.
Timing uncertainties can arise from data propagation variations and/or clock arrival variations. Data propagation variations include latching invalid data when the data has not settled at the register latch. Clock arrival variations include clock frequency fluctuations (jitter) and/or register-to-register clock edge arrival variations (skew). Timing uncertainties can be caused by such things as ambient chip conditions (e.g., local temperature induced circuit variations or circuit heat sensitivities), power supply noise, and chip process variations.
IC designs allow for timing uncertainties by building design margin into the timing sequences. A conservatism factor is applied to the expected timing to account for the timing uncertainties, with a larger conservatism factor required when larger timing uncertainties. Characterization of the timing uncertainties can avoid building unnecessary margin into the timing sequences.
Present systems for timing uncertainty measurement employ a string of latches to measure the timing uncertainty for a single data signal, such as a single clock or single data string. The edge of the data signal passes through the string of latches and triggers the latches. The timing of the edge can be determined from the state of the latches. It is often desirable to measure timing uncertainties for a number of data signals individually or simultaneously. Unfortunately, present systems require one dedicated string of latches for each data signal to be tested or a multiplexer to switch the data signal into a latch string. Use of multiple dedicated latch strings to measure multiple data signals requires use of valuable IC area and increases the cost of ICs. Use of a multiplexer reduces measurement sensitivity, requiring more margin to be built into the timing sequences and reducing performance. The problems of the present systems become worse as the number of data signals to be measured increases.
Present systems for timing uncertainty measurement are also inflexible. The length of the sampling window, i.e., the number of latches in the latch strings, is fixed. The timing uncertainty measurement uses all the latches, regardless of the length of the sampling window required. In addition, the sampling window is of fixed length and cannot be shared as several shorter sampling windows to measure a number of data signals simultaneously.
It would be desirable to have a circular edge detector that would overcome the above disadvantages.